(TBench) 2.2 Create a Project to hold the MUT

First, create a project file to hold the model under test. This will allow WaveFormer to extract the information necessary to instantiate the model under test inside the testbench and extract the input and output ports from the model under test. The model under test in this tutorial is a Verilog file, so we will be generating a Verilog test bench, but the diagram and the design flow is the same for a VHDL test bench and you can generate a VHDL test bench from the extracted signal information.

Non-Libero users create a SynaptiCAD Project and add the Model Under Test:

•Choose Project > New Project menu function to open the New Project Wizard dialog.

•In the Project Name box, type in reactivetut as the name of the project. This will become both the name of the project and the directory where the project and associated files are stored.

•Choose Verilog as the Project Language.

•Click the Finish button to create the project and close the dialog.

project_for_rtb_tut

•In the Project window, under the Source Files section, right click and choose Copy New Source Files from the context menu. The picture shows WaveFormer's interface. BugHunter and TestBencher projects have a User Source Files folder that you can right click on. This will open a file open dialog.

project_copy_mut

•Select mymut.v from the SynaptiCAD\Examples\TutorialFiles\ReactiveTestBench directory and close the dialog to copy the file to the project directory.

project_finished

Actel Libero users only:

Create a project inside Libero following the steps in the Libero documentation, add the source file mymut.v from the SynaptiCAD\Tutorials\ Reactive Test Bench directory, and launch WaveFormer Lite. This will automatically create a WaveFormer project file and add your source files to that project.

Investigate the Model Under Test

•In the Project window, double click on the mymut.v to open an Editor window which displays the model under test source code.

editor_mymut

We will use a simplified version of a PCI slave device as the model to be tested. No experience with PCI is required to perform and understand this tutorial. There is no arbitration, the MUT responds to all addresses, and the only valid commands are single reads and writes. It contains a memory that can be written to and read from and has the following ports (all control signals are active low):

CLK (input): the mymut device is clocked on the positive edge

FRAME (input): indicates start of transaction.

WRITE (input): indicates write transaction.

IRDY (input): stands for initiator ready. Indicates when the master device is ready for transaction to complete (the master will be the test bench in this case).

TRDY (output): stands for target ready. During a write, this indicates that the MUT has finished writing data to it's memory. During a read, this indicates that the MUT has read the data from memory and put it on the DATA bus.

ADDR (output): Address to write to or read from.

DATA (inout): Data to write to memory or data that is read from memory.

Each transaction consists of an address cycle and data cycle. During the address cycle, the WRITE and ADDR signals must be valid. During a write data cycle, the DATA signal must be valid before IRDY is asserted. Then the MUT indicates that it is finished storing the data by asserting TRDY. During a read data cycle, the MUT must drive DATA before asserting TRDY. Then, the master asserts IRDY when it is finished reading the data. Once IRDY or TRDY is asserted, they must remain asserted until the transaction is finished which is indicated by the de-assertion of FRAME.