(TBench) 3.9 Add Transaction Calls to the Sequencer Process

Inside the primary template file for the project is a Sequencer Process. This process is the place in the top-level test bench that defines the order in which the timing transactions are applied to the model under test. By using the Insert Diagram Calls dialog, you can construct the testbench by writing little to no code.

Open the Transaction-Level Model for the main Test Bench:

•In the Project window, double click on the Transaction-Level Model folder to open an editor window with the sramtest template file.

sequencer

Find the Transaction Sequencer in the Component Model:

•Scroll down in the sramtest editor window near the end of the file until you find the Transaction Sequencer comment block. The comment changes depending on the code generation language.

Sequencer_code_comment

Open the Insert Diagram Calls Dialog:

•Click in the sramtest editor window below the Transaction Sequencer comment (as shown above) so that the blinking cursor is in the place where the apply statement should be added.

•Right-click in the editor window and select Insert Diagram Calls to open the Insert Diagram Subroutine Call dialog.

insertDiagramSubroutineCall-sramtest

•Arrange the windows so you can see the editor and the dialog at the same time.

Insert the Apply calls:

The Insert Diagram Subroutine Calls dialog generates diagram apply calls so you do not need to memorize the function syntax. Each timing diagram can generate several task calls:

•Apply runs the transaction in a blocking mode so that no other transactions will run until this one is done.

•Apply-nowait runs the transaction concurrently with other transactions.

•Abort stops a running transaction.

•The Post calls are supported only in VHDL. A Post call schedules a transaction for future execution by placing it into a Transaction Manager queue (instead of immediately applying the transaction). The Transaction Manger must be enabled as described in Section 7.3 Transaction Manager Overview for these calls to operate. We will not be using the Post calls in this tutorial.

The Master/Slave Diagram Setting determines how many times a transaction executes. Master Transactors, like the Read, Write, and Initialize diagrams run once and stop. Slave Transactors like the Global Clock Generator run in a looping mode until an Abort call is received. You will first start the clock, initialize the control signals, write to the SRAM, read from the SRAM twice, and then abort the clock.

•Double click on the CLK_generator insert the statement into the Sequencer Process. Since this is a slave diagram (indicated by the black arrow), the default state is Apply-nowait, because most of the time slave diagrams will run concurrently with other diagrams.

•Double click on the tbinitialize entry. Since this is a master diagram, the default state is Apply, because usually Master diagram run in blocking mode.

•Double click on the tbwrite entry.

•Double click on the tbread entry TWO times to insert the code to add two read calls.

•Select CLK_generator entry, choose Abort radio button, and then press the Insert button to insert the code. This will add the abort call to stop the clock generator. Without this call, YOUR SIMULATION WOULD CONTINUE TO RUN FOREVER since the clock wouldn't stop.

•Close the Insert Diagram Subroutine Call dialog.

•The apply calls should look similar to the following code block. Different languages may have extra parameters.

Sequencer_apply_calls

Edit the State Values of the Write and Read Apply calls:

Edit the write and read Apply code lines and replace the state variable names with actual variables that will be passed into the timing diagrams. The comment lines are there to document the parameter variable names. Note: The code to be entered is bold.

•For Verilog type:

Apply_tbwrite('hF0, 'hAE);

Apply_tbread('hF0, 'hAE);

Apply_tbread('hF0, 'hEE);

•For VHDL type:

Apply_tbwrite(tb_Control, tb_LocalBfmPath, x"F0", x"AE");

Apply_tbread(tb_Control, tb_LocalBfmPath, x"F0", x"AE");

Apply_tbread(tb_Control, tb_LocalBfmPath, x"F0", x"EE");

•For OpenVera type:

tb_tbwrite.ExecuteOnce('hF0, 'hAE);

tb_tbread.ExecuteOnce('hF0, 'hAE);

tb_tbread.ExecuteOnce('hF0, 'hEE);

Notice that the tbwrite apply statement writes the hex value AE to memory cell F0. The tbread diagram calls will then read the value from the same memory cell. The data values provided in the tbread diagram calls will be used to compare with the actual value. The first call to tbread will expect to find a value of hex AE in the address F0. The second call to tbread will expect to find the hex value EE instead. This will cause the sample to report an error during the second execution of tbread.

•Save the top-level template file by right-clicking in the editor window and selecting Save.

In addition to these task calls, you can also place HDL code in the sequencer. One example where this would be useful is if you wish to place conditions on whether or not a timing transaction is called, or on the parameter values that you wish to have applied.

An alternative method to placing transaction calls in the sequencer process is to create a file external to the bus-functional model with transaction calls and during simulation read the transaction calls from a file (see Section 7.3: Transaction Manager Overview in the online TestBencher Manual).