(TBench) 1.1 Load the Tutorial Timing Diagram |
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(TBench) 1.1 Load the Tutorial Timing Diagram |
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(TBench) 1.1 Load the Tutorial Timing Diagram |
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(TBench) 1.1 Load the Tutorial Timing Diagram |
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This tutorial requires a full version license of WaveFormer Pro, BugHunter Pro, or Test Bencher Pro because you will need to generate the test bench and save files. Timing Diagrammer Pro cannot generate test benches. To obtain a temporary license for evaluation purposes, complete the form under the Help > Request License menu item and contact our sales department.
Run WaveFormer Pro, BugHunter Pro, or Test Bencher Pro:
•Run one of the above programs from the Start Menu. |
Load the starting Timing Diagram:
•Select the File > Open menu option and load the file tuthdl.btim from the SynaptiCAD\Examples\TutorialFiles\AdvancedHDLStimulusGeneration directory. |
The first signal, CLK0, is a clock with a period of 50ns. The second signal, SIG0, is a waveform that contains all of the graphical states available in WaveFormer Pro. The third signal, VirtualBus, is a waveform drawn with valid and tri-state segments that you will add values to in the next section. The blue icons pointing to the left mean that the signals are outputs of the test bench and will be exported when you generate the code.
Save the starting Timing Diagram:
•Select the File > Save As menu option and save the timing diagram as test.btim (this will keep the original file intact). |