(Sim) 2.4 Export Waveforms to VHDL |
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(Sim) 2.4 Export Waveforms to VHDL |
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(Sim) 2.4 Export Waveforms to VHDL |
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(Sim) 2.4 Export Waveforms to VHDL |
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In the first steps of this tutorial, we created a project file and pressed the Extract MUT Ports button. This also determined the model under test module. The project must remain open during the export of the btim file in order for the model under test to be instantiated in the stimulus file. If the source files in the project contained multiple modules that could be the top level MUT instance, you would need to select the top level instance in the project window by right clicking on the desired top level instance.
Generate the VHDL test bench by exporting the timing diagram file.
•Choose the Import/Export > Export Timing Diagram As menu option to open the Export As dialog. •Set the Save As Type drop-down to VHDL w/Top Level Test Bench (*.vhd). This creates a VHDL file called add4test.vhd containing the stimulus and instantiates a copy of the model under test. |
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•Once the file is generated it is also loaded into the Report window so that you can see the generated code. If you cannot see the Report window, then choose the Window > Report menu option. |
