The Report window simulation.log  tab displays the default log file for the simulator. TestBencher automatically writes a message to the log file each time a transaction starts and stops. The clocked SRAM contains code to display a message each time it performs a read or write. We also added a sample parameter to the Read Cycle, and set it to generate an error message when the data from the SRAM does not match the expected value.

Examine the log file:

•In the Report window, open the simulation.log tab and display the following results:

sim> run

SIM: TB> Note: In "sramtest_CLK_generator" at 0.000ns: Executing LOOPING

SIM: TB> Note: In "sramtest_tbinitialize" at 0.000ns: Executing ONCE

SIM: TB> Note: In "sramtest_tbinitialize" at 50.000ns: Execution DONE

SIM: TB> Note: In "sramtest_tbwrite" at 50.000ns: Executing ONCE

SIM: In clksram at 150.000ns: Writing ae to address f0

SIM: TB> Note: In "sramtest_tbwrite" at 350.000ns: Execution DONE

SIM: TB> Note: In "sramtest_tbread" at 350.000ns: Executing ONCE

SIM: In clksram at 450.000ns: Reading ae to address f0

SIM: TB> Note: In "sramtest_tbread" at 650.000ns: Execution DONE

SIM: TB> Note: In "sramtest_tbread" at 650.000ns: Executing ONCE

SIM: In clksram at 750.000ns: Reading ae to address f0

SIM: TB> Error: In "sramtest_tbread" at 850.000ns: Sample SAMPLE0_process sampled signal: DBUS

SIM:       Expected state: ee ; Detected state: ae

SIM: TB> Note: In "sramtest_tbread" at 950.000ns: Execution DONE

SIM: TB> Note: In "sramtest_CLK_generator" at 950.000ns: Execution DONE

SIM: TB> Total Warnings =           0

SIM: TB> Total Errors =           1

Simulation finished due to event queue exhaustion.

Simulation time: 0.2 s (CPU time: 0.2 s)

sim> start_corba_msg_pump

sim> exit

Process exited with code 0.

•Notice that the clock generator starts at time zero and continues until the end of the simulation when the abort call is issued.

•The initialization diagram also starts executing at time zero and blocks the next transaction until it is complete.

•The write diagram starts next and writes a value to the SRAM. The SRAM acknowledges that is writing the value to the specified address.

•The first read diagram executes successfully.

•The second read diagram throws a warning because the expected value did not match the value from the MUT. We purposely passed in a bad expected data value so we could see how the sample throws the error.

•Next the abort call to the clock stops the clock transaction and ends the simulation.