Verilog contains two system tasks (commands), $display and $monitor, that can be included in Verilog source files for debugging purposes. $display acts like a C-language printf statement which prints to the simulation log file simulation.log whenever it is executed by the Verilog simulator. $monitor is similar, but it automatically prints to the log file whenever any of the signals listed in this command change state. The SRAM model file sram.v contains two $display statements that output the address and data values for the SRAM whenever the SRAM is read from or written to (you can view the $display commands in sram.v in the Report window). You can see the output of the $display commands by viewing simulation.log in the Report window. Each time the SRAM performs a read or write a message is sent to the log file.