(TD) 6.4 Checking for Simulation Errors |
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(TD) 6.4 Checking for Simulation Errors |
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(TD) 6.4 Checking for Simulation Errors |
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(TD) 6.4 Checking for Simulation Errors |
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If you check the simulator log file, simulation.log 
in the Report window, you will see an error message reporting that DONE is not declared. The log file also reports the lines in the WaveFormer-generated Verilog source code file where this error occurred. The WaveFormer-generated source file will have the same filename as your diagram, but with a file extension of .v instead of .btim (so if your diagram is untitled.btim, the source code file is untitled.v). This source file is automatically opened by the Report window whenever WaveFormer Pro generates this file (by default this occurs every time you make a change to your design while simulating signals).
View the HDL lines where the errors occur:
1. Check the log file for the line number at which the error(s) occurred. In the Report window, click on the simulation.log tab . When we ran the simulator, our error occured at line number 57 (your run may be different) , as indicated by the error message: C:\SynaptiCAD\UNTITLED.v: L57: error: 'DONE' not declared
2. Click on the tab for the *.v file at the bottom of the Report window. This will open your source file in the Report window.
3. Click inside the Report window, and press <Ctrl>-G. This brings up the Go To Line window. Enter 57 as the line number you wish to jump to, and press OK. 4. As expected, these lines show the HDL code that simulates the IDLE and READ signals. |
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NOTE: Do not make changes in this source file as your changes will automatically be overwritten the next time a simulation is performed; instead, we will make the appropriate changes in the Diagram window and Signal Properties dialog.
