This tutorial demonstrates the basic timing diagram editor features. It teaches you how to draw timing diagrams using delays, setups, clocks and part libraries and how to use timing diagrams to help detect timing errors in digital designs. It also covers the waveform editing features, measurement and quick access buttons.

You will draw the timing diagram for a circuit that divides the clock frequency in half. Both the flip-flop and the inverter have propagation times that delay the arrival of the Dinput signal. If Dinput is delayed too long it will violate the data-to-clock setup time (Dsetup). This increases the risk of the flip-flop failing to clock in the data and may lead to the flip-flop entering a metastable state.

Above is an image of the timing diagram and parameter table that you will enter during the tutorial. The first thing you may notice is the gray signal transitions caused by the min/max values of the component delays. The gray areas of the signal transitions are uncertainty regions, which indicate that the signal may transition any time during that period. This is a little disconcerting especially if you have been using a low-end simulator that cannot compute both min and max at the same time. This representation shows the entire range of possible circuit performance, so that there won't be any surprises during production when you get components at extreme ends of their tolerance range.