1.13 Escaping Signal Names with Strange Characters

Signals normally have limits on what ASCII characters can be used in their names. For example, most non-alpha numeric characters such as &,!, etc. are not allowed in a signal name by default. To enable the use of such characters, you must escape the signal name with an appropriate pair of escape characters. Signal names can be escaped using either the VHDL or the Verilog escaping style, depending on what escaping style you have set for the diagram.

Setting the Escaping Style for a Timing Diagram

By default, a newly created timing diagram will use VHDL-style escaping. To change the style do the following:

•Select the View > Set Signal Escaping Style menu and choose either the VHDL or Verilog option.

Changing the escaping style will also change how any existing escaped signal names are displayed to match the new escaping style.

VHDL and Verilog Escaping Examples

•To escape using VHDL-style escaping, begin and end the signal name with a backslash character "\".	\MySignal&1\
•To escape using Verilog-style escaping, begin the signal name with a backslash character and end the name with a space character " " (Note the space character is not visible).	\MySignal&1

Escaping Hierarchical Signal Names

If your timing diagram contains hierarchical signal names such as to&p.leaf1.sig&nal1, each hierarchical level that contains non-alpha numeric characters must be escaped separately.

•For example, with VHDL-style escaping, this name should be entered as shown.	\to&p\.leaf1.\sig&nal1\
•Or, with Verilog-style escaping, the name should be entered as shown. Note the space after the p in the first hierarchy level of the name. There is also an invisible space after the 1 in the last part of the name.	\to&p .leaf1.\sig&nal1