In the initial stages of your design you will be performing "functional" simulations to ensure the logic in your circuit operates correctly. After your FPGA or ASIC tools generate a layout for your gate-level design, you may want to perform a final simulation with back-annotated timing information generated during the layout process to account for real world interconnect and gate delays. This "timing" simulation is often used as a final check to ensure that unexpected delays generated during the layout process don’t create timing violations in your design. The layout tools will create a Standard Delay File (SDF) that includes this timing information. By including this timing information, the model can be tested based upon these propagation delays. Note, this type of timing simulation is often unnecessary if you use a static timing analysis tool to verify the critical paths in your design meet the timing constraints of your design.

Including an SDF file using VeriLogger

An SDF can be produced for any module in the hierarchy of your project. For example, if you are modeling a board-level design that contains an FPGA, your FPGA tools will probably produce an SDF file for the laid out gate level model of the FPGA. To include the timing from this file into your design, add an $sdf_annotate command in the FPGA module whose timing is to be modified. Include the bolded lines in the example FPGA module shown below to tell the simulator to read the SDF timing information:

module MyFPGA(ports…)

//port declarations…

initial

    begin

    $sdf_annotate("mydesign.sdf");

    end

//other code…

endmodule

(Note: If you have an initial block already in the module to be annotated, you can include the $sdf_annotate line in the existing block. Also note that "mydesign.sdf" shown above should be replaced with whatever filename your tool generated. The file extension .sdf should be used.)

Annotating with Multiple SDF files

More than one SDF file can be annotated. Each call to the $sdf_annotate task annotates the design with timing information from an SDF file. Annotated values either modify (INCREMENT) or overwrite  (ABSOLUTE) values from earlier SDF files. Different regions of a design can be annotated from different SDF files by specifying the region s hierarchy scope as the second argument to $sdf_annotate.