Step 5: Draw a Test Bench (optional)

If your top-level component has input ports, BugHunter can take drawn waveforms and generate a test bench model that can be used to test your model. The VeriLogger Basic Verilog Simulation tutorial demonstrates this feature. Each time a simulation is run (see Step 7: Simulate and Debug), BugHunter will create a test bench component from the drawn waveforms. A wrapper component that hooks up the test bench component to the design model is created at the same time.

Draw a Stimulus Test Bench for unit level testing:

•Make sure the simulation mode is set to Debug Run, rather than Auto Run, so that the simulator does not re-simulate while you are drawing.

•Press the Parse MUT button to extract the port signal names and sizes and put them in the Stimulus and Results diagram. This will also populate the project window with the hierarchical.

•Draw waveforms on the output signals, which will be drawn in black.

•If you have the Reactive Test Bench option then you may also wish to draw waveforms on input signals to indicate the expected inputs to the testbench (or outputs from the model under test), and these waveforms will be drawn in blue.

Changing the Model Under Test:

•The Parse MUT function makes a guess as to which model is the model under test and displays that model with single brackets, <>, underneath in the Models Under Test folder.

•To pick a different model under test, first right click on the MUT and choose Unset Current Model Under Test, and then right click on a different model under the User Source Files list and pick Set as Model Under Test. Multiple models under test can also be specified.

•Then press Parse MUT button to re-populate the Stimulus and Results diagram.