5.2 Preparing Verilog Source files |
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5.2 Preparing Verilog Source files |
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5.2 Preparing Verilog Source files |
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5.2 Preparing Verilog Source files |
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Before using the command line simulator you may want to add statements to the Verilog source code to generate simulation display statements. Signals that were watched in the graphical simulator will not automatically generate output in the command line simulator.
There are several Verilog statements that will generate output:
•The $monitor system task is used to continuously monitor a signal and produce an output message every time the signal changes. $monitor("Counter = %d", count); •The $display system task is used to print text messages and look at values on signals. The $display statements write the results to the verilog.log file. This statement is similar to a debug statement used to debug program flow in a standard programming language. See the Verilog Language Overview for more information on the syntax. An example of a display statement used inside a module is: $display("Counter = %d", count); •The $dumpvars, $dumpfile, $dumpall, $dumpon, and $dumpoff system tasks are used to save waveform data in to a value change dump (VCD) file. The VCD format is a standard Verilog file format that can be used with external waveform viewers, static timing analyzers, or VeriLogger's graphical display. See the Verilog Language Overview for more information on the syntax of these statements. |