Timing Diagrammer Pro	WaveFormer Pro	TestBencher Pro
Windows 3.1/95/NT pricing (go to the quote page to view the quantity discounts available)	$1,500	$2,250	$15,000
Bus-functional model generation for VHDL and Verilog
Multi-diagram test bench generation for VHDL & Verilog
Single-diagram test bench generation for VHDL & Verilog
Interactive HDL Simulator - simulates Boolean equations & registered logic with true min/max timing delays. Automatic re-simulation is triggered when inputs change.
Vector Waveform Input (in addition to graphical input)
Support for counter design
SPICE stimulus generation
Import VCD (Verilog change dump files) and VHDL simulator input
Temporal equation generator (good for DSP waveforms)
Signals support 7 different graphical waveform states and data format
Graphical timing parameters: delays, setups, holds, and samples
Clocks with formulas and bus support
Min-only and max-only delays
Color-coded, multiple delays on a single edge
Realistic databook documentation
Documentation support for EPS, FrameMaker MIF, WFM metafiles, CGM metafiles, Enhanced metafiles, copy-to-clipboard
Multiple Undo
TDML Support
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SynaptiCAD's VeriLogger Pro, WaveFormer Pro, and TestBencher Pro products can generate VHDL and Verilog test benches graphically from timing diagrams. Each product provides a different level of test bench generation. Click Here to figure out which level of test bench generation meets the type and complexity of your testing needs.